1. Technical Field
The embodiments described herein relate to a semiconductor memory apparatus. More particularly, the embodiments described herein relate to an internal voltage testing circuit.
2. Related Art
A Conventional semiconductor memory apparatus receives external voltage to generate desired voltage having a predetermined level. At this time, the voltage generated in the semiconductor memory apparatus is referred to as internal voltage.
During a test mode, an internal voltage generation circuit generates the internal voltage according to a level of external reference voltage. If the test mode is completed, the internal voltage generation circuit generates the internal voltage according to a level of internal reference voltage.
In a semiconductor memory apparatus having the internal voltage generation circuit as described above, it is possible to monitor a level of the internal voltage, which is generated according to the level of the external reference voltage, in a test step prior to a packaging step. After the test step, the internal voltage generation circuit detects a level of external reference voltage, which allows the internal voltage to have a target level, and fixes the detected external reference voltage level as a level of internal reference voltage.
After packaging the semiconductor memory apparatus, it is impossible to monitor levels of the internal voltage and the internal reference voltage generated in the semiconductor memory apparatus. Thus, if the semiconductor memory apparatus has been packaged, it is difficult to analyze and solve the problems caused by the failure of the internal voltage.